NXP Semiconductors /MIMXRT1011 /SNVS /LPSVCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPSVCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SV0_EN_0)SV0_EN 0 (SV1_EN_0)SV1_EN 0 (SV2_EN_0)SV2_EN 0 (SV3_EN_0)SV3_EN 0 (SV4_EN_0)SV4_EN 0 (SV5_EN_0)SV5_EN

SV4_EN=SV4_EN_0, SV3_EN=SV3_EN_0, SV5_EN=SV5_EN_0, SV0_EN=SV0_EN_0, SV2_EN=SV2_EN_0, SV1_EN=SV1_EN_0

Description

SNVS_LP Security Violation Control Register

Fields

SV0_EN

Security Violation 0 Enable This bit enables Security Violation 0 Input

0 (SV0_EN_0): Security Violation 0 is disabled in the LP domain.

1 (SV0_EN_1): Security Violation 0 is enabled in the LP domain.

SV1_EN

Security Violation 1 Enable This bit enables Security Violation 1 Input

0 (SV1_EN_0): Security Violation 1 is disabled in the LP domain.

1 (SV1_EN_1): Security Violation 1 is enabled in the LP domain.

SV2_EN

Security Violation 2 Enable This bit enables Security Violation 2 Input

0 (SV2_EN_0): Security Violation 2 is disabled in the LP domain.

1 (SV2_EN_1): Security Violation 2 is enabled in the LP domain.

SV3_EN

Security Violation 3 Enable This bit enables Security Violation 3 Input

0 (SV3_EN_0): Security Violation 3 is disabled in the LP domain.

1 (SV3_EN_1): Security Violation 3 is enabled in the LP domain.

SV4_EN

Security Violation 4 Enable This bit enables Security Violation 4 Input

0 (SV4_EN_0): Security Violation 4 is disabled in the LP domain.

1 (SV4_EN_1): Security Violation 4 is enabled in the LP domain.

SV5_EN

Security Violation 5 Enable This bit enables Security Violation 5 Input

0 (SV5_EN_0): Security Violation 5 is disabled in the LP domain.

1 (SV5_EN_1): Security Violation 5 is enabled in the LP domain.

Links

() ()